FPGA Developer | FPGA Design | FPGA/ASIC Hardware Verification | Twin Cities, MN (Onsite) Job at Stellent IT LLC, Minnesota

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  • Stellent IT LLC
  • Minnesota

Job Description

##Job : - 1

Hi,

Position: FPGA Developer

Location: Twin Cities, MN (Onsite)

Duration: 12+ Months

Interview Mode: Video

JD

FPGA Developer -Active Secret Clearance

Skills required:
1. Should have worked on USRP N310/X310 (N3xx/X3x0)
2. In-depth Knowledge of FPGA Architecture
3. Able to write own RTL custom HDL or drops in IP
a) VHDL, Verilog, System,Verilog, Vivado HLS
b) Xilinx IP, Vivado Block Diagram
4. Should have developed RFNoC Block
5. Have working knowledge of USRP Hardware Driver (UHD)

##Job : - 2

Position: FPGA Design

Location: Twin Cities, MN (Onsite)

Duration: 12+ Months

Interview Mode: Video

Full job description

VHDL, Xilinx exp, Vivado tools, Versal Chipset experience a plus

Aerospace/Defense experience a plus

**Active Secret Clearance Needed

  • Responsible for high-speed multimillion-gate and multi-clock domain FPGA designs.
  • Experience in translation of hardware requirements into a proven, scalable, system architecture and design.
  • Responsible for designing from initial specifications to silicon.
  • Experience with Xilinx / Altera FPGAs, embedded multi-processor interface architectures, Verilog/VHDL RTL design, verification, FPGA synthesis/timing, lab validation planning/execution.

##Job : - 3

Position: FPGA/ASIC Hardware Verification

Location: Twin Cities, MN (Onsite)

Duration: 12+ Months

Interview Mode: Video

Full job description

UVM, SystemVerilog,

Aerospace/Defense experience a plus

**Active Secret Clearance Needed

Required skills:

  • As a Design engineer should be able to develop design specs, HDL based RTL
  • Strong knowledge on Digital design concepts with RTL implementation (Verilog/VHDL)
  • Experience with FPGA/ASIC tool flows for Logic Synthesis, STA and Frontend Design.
  • Expertise in RTL top level integration and should have excellent debugging skills.
  • As a Verification engineer Working on full chip Verification and OVM/UVM Methodology,
  • System Verilog is a must with 3+ years of work experience,

Niranjan Kumar | Technical Recruiter

Email: niranjan@stellentit.com

Stellent IT | office :

Job Tags

Work experience placement, Work at office,

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