##Job : - 1
Hi,
Position: FPGA Developer
Location: Twin Cities, MN (Onsite)
Duration: 12+ Months
Interview Mode: Video
JD
FPGA Developer -Active Secret Clearance
Skills required:
1. Should have worked on USRP N310/X310 (N3xx/X3x0)
2. In-depth Knowledge of FPGA Architecture
3. Able to write own RTL custom HDL or drops in IP
a) VHDL, Verilog, System,Verilog, Vivado HLS
b) Xilinx IP, Vivado Block Diagram
4. Should have developed RFNoC Block
5. Have working knowledge of USRP Hardware Driver (UHD)
##Job : - 2
Position: FPGA Design
Location: Twin Cities, MN (Onsite)
Duration: 12+ Months
Interview Mode: Video
Full job description
VHDL, Xilinx exp, Vivado tools, Versal Chipset experience a plus
Aerospace/Defense experience a plus
**Active Secret Clearance Needed
##Job : - 3
Position: FPGA/ASIC Hardware Verification
Location: Twin Cities, MN (Onsite)
Duration: 12+ Months
Interview Mode: Video
Full job description
UVM, SystemVerilog,
Aerospace/Defense experience a plus
**Active Secret Clearance Needed
Required skills:
Niranjan Kumar | Technical Recruiter
Email: niranjan@stellentit.com
Stellent IT | office :
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